
\begin{abstract}
We describe a family of power-aware models of multicore processors that departs from traditional models, which assume that cores contribute power as independent entities.
In our approach, we remove this independence assumption, showing that it both better reflects current processors and also captures the subtle interactions between the computational workload and the underlying hardware.
We evaluate these models on five Intel multicore processors covering four major microarchitectures (Nehalem, Sandy Bridge, Ivy Bridge and Haswell) using SPEC 2006 benchmarks.
We systematically explore the model family, deriving a sequence of models that give progressively better fits, and we analyze them in detail.
Our best model yields an average predicted error as low as $2.4\%$.
We show how to use the models to develop an algorithm for setting core operating speeds to satisfy both quality-of-service and power-bound constraints.

 %optimize the cores' frequency distribution to keep the same throughput with reduced power supply (as large as $37\%$ based on our experimental results) or improve the throughput with the same power budget. Experimental results of SPEC 2006 on Sandy Bridge multicore processor show that the maximal residual ratio of our model is less than $10\%$ (the average residual ratio is less than $1\%$ ) and  more than $95\%$ samples their residual ratios are less than $5\%$.  We have evaluated our power model with single and mixed benchmarks running on part or all the cores of one processor. Our model can predict the power perfectly if only the given workload can have stable average power.
%We theoretically demonstrate the correctness and efficiency of our method.
%Low power and/or energy consumption is a requirement not only in embedded systems that run on batteries or have limited cooling capabilities, but also in desktop and mainframes where chips require costly cooling techniques

\end{abstract}
